Module Design in VHDL

In today’s blog post, we will cover the basics of module design with VHDL (Very High-Speed Integrated Circuit Hardware Description Language). VHDL is a powerful hardware description language widely used in FPGA and ASIC designs. In this article, we will examine three main modeling methods for module design in VHDL: Structural Modeling, Behavioral Modeling, and Dataflow Modeling. We will explain each modeling method and support them with examples.

Structural Modeling

Structural modeling defines how the sub-modules of a design are connected to each other. This type of modeling is used to identify the components of a larger system and their connections. This approach allows the design to be structured hierarchically.

Structural Modeling Example

Let’s consider a 4-bit full adder design. This design consists of four 1-bit full adder modules. Each 1-bit full adder is connected with two inputs and one output. The VHDL code for this structural modeling is given below:

library ieee;
use ieee.std_logic_1164.all;

entity fulladder4bit is
    port (
        a   : in std_logic_vector(3 downto 0);
        b   : in std_logic_vector(3 downto 0);
        cin : in std_logic;
        sum : out std_logic_vector(3 downto 0);
        cout: out std_logic
    );
end entity fulladder4bit;

architecture structural of fulladder4bit is
    component fulladder1bit
        port (
            a    : in std_logic;
            b    : in std_logic;
            cin  : in std_logic;
            sum  : out std_logic;
            cout : out std_logic
        );
    end component;

    signal c : std_logic_vector(3 downto 0);
begin
    fa0: fulladder1bit port map(a(0), b(0), cin, sum(0), c(0));
    fa1: fulladder1bit port map(a(1), b(1), c(0), sum(1), c(1));
    fa2: fulladder1bit port map(a(2), b(2), c(1), sum(2), c(2));
    fa3: fulladder1bit port map(a(3), b(3), c(2), sum(3), cout);
end architecture structural;

Unwritten rule: Entity and architecture names should be written in lowercase letters. Signal and variable names should also be written in lowercase letters. Constants and generic constants should be written in uppercase letters.

Behavioral Modeling

Behavioral modeling defines the internal behavior of a system and how it works. This type of modeling specifies how inputs are processed and how outputs are generated. Behavioral modeling is used to design at an algorithmic level.

Behavioral Modeling Example

Let’s consider a 4-bit counter design. This counter increments by one on each clock pulse and displays the current count at the output. The VHDL code for this behavioral modeling is given below:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity counter4bit is
    port (
        clk : in std_logic;
        rst : in std_logic;
        q   : out std_logic_vector(3 downto 0)
    );
end entity counter4bit;

architecture behavioral of counter4bit is
    signal count : std_logic_vector(3 downto 0) := "0000";
begin
    process(clk, rst)
    begin
        if rst = '1' then
            count <= "0000";
        elsif rising_edge(clk) then
            count <= count + 1;
        end if;
    end process;
    q <= count;
end architecture behavioral;

Unwritten rule: The reset signal should be specified as “rst” or “rstn”. The clock signal should be specified as “clk”. Care should be taken with alignments to ensure the code appears neat. Only one of the “numeric” or “arith” libraries should be used in the code.

Dataflow Modeling

Dataflow modeling defines how data flows and is processed. This type of modeling is generally used to specify parallel operations and timing requirements.

Dataflow Modeling Example

Let’s implement a 4-bit adder using dataflow modeling. This adder takes two 4-bit inputs and a carry input and produces a 4-bit sum and a carry output. The VHDL code for this dataflow modeling is given below:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity adder4bit is
    port (
        a   : in std_logic_vector(3 downto 0);
        b   : in std_logic_vector(3 downto 0);
        cin : in std_logic;
        sum : out std_logic_vector(3 downto 0);
        cout: out std_logic
    );
end entity adder4bit;

architecture dataflow of adder4bit is
begin
    process(a, b, cin)
    begin
        variable temp : std_logic_vector(4 downto 0);
        temp := ("0" & a) + ("0" & b) + cin;
        sum <= temp(3 downto 0);
        cout <= temp(4);
    end process;
end architecture dataflow;

Unwritten rule: “std_logic_vector” type variables should be defined using the “downto” keyword. Comments can be in Turkish or English. Care should be taken with alignments to ensure the code appears neat.

In this article, we examined three main modeling methods for module design in VHDL: Structural Modeling, Behavioral Modeling, and Dataflow Modeling. Each modeling method has different advantages and usage areas. By using these methods, you can perform complex hardware designs more effectively and efficiently.

In our next article, we will cover more advanced topics in VHDL. Stay tuned!

If you have any questions or topics you would like to see detailed, please share them in the comments.

This article was first published on LinkedIn on 6 August 2024.