Basic Concepts of VHDL

VHDL (VHSIC Hardware Description Language) is a powerful hardware description language used for the design and modeling of digital systems. In this section, we will cover concepts such as entities, architectures, signals, variables, libraries, and packages that form the fundamental building blocks of VHDL. Our aim is to provide readers with an understandable presentation of the basic principles and usage of VHDL, thereby establishing a solid foundation for digital circuit design. This will enable successful and efficient results in projects carried out with VHDL.

Entities and Architectures

Unwritten Rule – Only one “entity” and “architecture” should be defined within an HDL file (vhd/v/sv). 🙂

Unwritten Rule – All special characters, including “entity” and “architecture” names, should be written in lowercase. 🙂

Explanation of Entity and Architecture Concepts

Entities: An entity in VHDL is the section where the inputs and outputs of a digital circuit are defined. An entity specifies how the circuit interacts with the outside world. Every VHDL code starts with an entity declaration, and within this declaration, the input and output ports are defined.

Unwritten Rule – Ports that are related to each other should be grouped within an entity. 🙂

-- In this example, an entity named AndGate is defined. The input ports are a and b, and the output port is y.

entity AndGate is
    port (
        -- input
        a : in std_logic;
        b : in std_logic;
       -- output
        y : out std_logic
    );
end entity AndGate;

Architectures: An architecture describes the internal operation of the ports defined by an entity. An architecture can be defined one or more times for an entity. This section includes the behavioral, dataflow, or structural descriptions of the circuit.

Unwritten Rule – “architecture” names should be written in lowercase. 🙂

-- This architecture definition combines the A and B inputs of the AndGate entity using an AND operation and assigns the result to the Y output.

architecture Behavioral of AndGate is
begin
    y <= a and b;
end architecture Behavioral;

Signals and Variables

Unwritten Rule – Signal and variable names should be written in lowercase. 🙂

Unwritten Rule – Signal constant and entity names should be meaningful according to the function of the block or signal. 🙂

Differences Between Signals and Variables

Signals: Signals are used in VHDL to facilitate data exchange between entities. Signals are data lines that are always present and can be continuously modified during circuit simulation.

-- This signal can be used within any process or architecture.

signal temp_signal : std_logic;

Variables: Variables are locally defined within a process block and are only valid within this process block. Variables are re-evaluated each time the process is executed and are only updated after the process is completed.

-- In this example, a variable named temp_var is defined and used within the process block. However, the use of variables is not recommended, and signals should be preferred.

process (clk)
    variable temp_var : std_logic;
begin
    if rising_edge(clk) then
        temp_var := '1';
        output <= temp_var;
    end if;
end process;

Libraries and Packages

Unwritten Rule – Library and package names should be written in lowercase. 🙂

Concepts of Libraries and Packages

Libraries: Libraries contain various packages and modules that will be used in VHDL designs. Libraries are defined with a specific name and are called at the beginning of the code with the library keyword.

-- In this example, the ieee library is called, and the std_logic_1164 package is used.

library ieee;
use ieee.std_logic_1164.all;

Packages: Packages in VHDL are configurations that include reusable components, data types, constants, and functions. Packages are defined as part of a specific design, and the contents of these packages can be used elsewhere.

-- In this example, a package named my_package is defined, and it contains a constant and a function. This package can be used in other VHDL codes.

package my_package is
    constant MY_CONSTANT : integer := 10;
    function my_function (a : integer) return integer;
end package my_package;

package body my_package is
    function my_function (a : integer) return integer is
    begin
        return a * MY_CONSTANT;
    end function my_function;
end package body my_package;

With these basic concepts, we have understood the building blocks of VHDL. To start learning VHDL and designing digital circuits, it is essential to have a good understanding of these concepts. In future writings, we will build upon this foundational knowledge and move on to more complex designs and applications.

This article was first published on LinkedIn on 17 July 2024.